With the development and expansion of computer terminal equipment, such as that employed in electronic point-of-sales terminals, the demand for terminals which are capable of performing a plurality of specialized tasks has resulted in the creation of equipment which contains a plurality of microprocessors, each of which may be tailored to perform one specific task within the overall system. Concomitant to this multi-processor configuration is the need for a communication scheme which affords rapid, real-time communications between the independent processors. In conventional systems, each processor, in addition to performing one dedicated function, has been burdened with the task of looking for intermodule communications to which it must respond.
Typically, data is placed on a common intermodule bus to which each processor module in the system is coupled. This data contains the address of a target module for whom the particular message is intended and all CPUs within the system decode the address portion of the message in order to ascertain for whom the data is intended. This means that all CPUs must continually look at the intermodule bus and decode data; yet, only that module for which the data is intended will respond. This conventional approach is time consuming, the microprocessor being inherently too slow to perform this task efficiently, and usually a great deal of software is required in order to distinguish between addresses or commands, and each CPU may be unnecessarily burdened.
Now, various attempts have been proposed to relieve the central processor of these communication channel monitoring duties. For example, the U.S. Pat. No. to Beausoleil et al. 3,400,372 describes a multi-data processing system wherein the interfacing of two processors is effected through a processor-to-processor adapter, which becomes coupled to each computer when an interprocessor communication is to proceed. This technique may be termed a quasi-third party control scheme since each processor communicates by way of the third party (the channel adapter) under CPU control. The system is limited in that it is strictly limited to interfacing two processors, the communication itself is dependent upon interrupt acknowledgement before proceeding and, once begun, both the transmitting processor and the receiving processor must suspend all other tasks until the message is complete.
The use of a third party interfacing scheme is also disclosed in the U.S. Pat. No. to Broderick et al. 3,483,520 which describes a "mail-box" technique of routing multi-processor communications. All communications are routed through a central control sub-system (CCS) which contains all the interfaces for the processors that form part of a "star" configured network. All communications depend on one element, the CCS, so that if it fails, all communications cease. Such an approach has obvious shortcomings.
The case of a common bus scheme to perform data transfers among individual modules units is described in the U.S. Pat. No. to Bergh et al. 3,820,079 which discloses a multiprocessing computer wherein communications within one computer are conducted by way of module control units, each of which communicates with other module control units. The modules themselves are not independent processors, however, and because of a priority scheme through which use of the bus is defined, intermodule communications are not guaranteed, but are subject to bus availability. This problem of bus-lockout also exists in the bus communication system described in the U.S. Pat. No. to Schlaeppi 3,480,914 which describes a scheme wherein individual bus adapters are employed for each processor. Each adapter or interaction control unit responds to commands appearing on the common bus transmitted from other adapters to permit seizure of the bus. It is not until an interaction control unit has completed its use of the bus that control of the bus may pass to another adapter.
A further system in which a common bus is used for multi-module coupling is described in the U.S. Pat. No. to Trantanella 3,470,542. However, rather than relate to communications between independent processors, this system is directed to the transmission of signals between module units such as keyboards, printers memory, etc.; at any given time, one of the modules assumes control of the entire system.
Thus, although various prior art systems include techniques developed to control communications between various units in a digital data handling system over a common communication channel, such systems have not provided an efficient scheme for guaranteeing communications between multiple processors over a common communication link, while also relieving the individual processors of having to continuously monitor the channel for communications, thereby impeding intended data processing functions.